The present invention relates to a video signal processing circuit for a video tape recorder (hereinafter called "VTR") and more particularly to a level clamping circuit used in the video signal processing circuit.
A video signal regeneration circuit in VTR includes a level clamping circuit for clamping a tip level of each synchronizing signal contained in a reproduced (playback) video signal at a predetermined level (hereinafter called "clamp level"). The VTR has not only a normal playback mode but special playback modes such as "STILL", "SLOW" and "QUICK" modes. A vertical synchronizing signal contained in the video signal reproduced in the special regeneration modes cannot be used for vertical synchronization of a television receiver. Therefore, a pseudo vertical synchronizing signal is prepared independently and is inserted in a special mode reproduced video signal. The tip level of the pseudo vertical synchronizing signal thus inserted is required to be aligned with the clamp level. For this purpose, the pseudo vertical synchronizing signal is inserted into the reproduced video signal at a stage before the level clamping circuit.
Normally, a television signal includes equivalent pulses of 1/2 horizontal period (1/2 H) during a vertical blanking (retracing) period, and a horizontal AFC (Automatic Frequency Control) circuit used in recent high-resolution television receivers also responds to the equivalent pulses to control a horizontal synchronizing oscillator, so that the oscillation frequency of the horizontal synchronizing oscillator is maintained constantly also during the vertical blanking period. Therefore, a pseudo vertical synchronizing signal is added with pulses at a cycle proportional to one horizontal cycle, e.g., at a 1/2 horizontal cycle.
However, the prior art merely inserts such a pseudo vertical synchronizing signal into the special mode reproduced video signal at a stage before the clamping circuit. For this reason, the pseudo vertical synchronizing signal is wholly clamped at the clamp level, the pulses at 1/2 horizontal cycles disappear. As a result, the horizontal AFC circuit does not operate and the horizontal synchronizing oscillator deviates from a predetermined oscillation frequency.